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d a t a sh eet product speci?cation file under integrated circuits, ic12 1997 nov 21 integrated circuits pcf8549 65 102 pixels matrix lcd driver
1997 nov 21 2 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 features single chip lcd controller/driver 65 row and 102 column outputs display data ram 65 102 bits on-chip: C generation of lcd supply voltage C generation of intermediate lcd bias voltages C oscillator requires no external components (external clock also possible) 400 khz fast i 2 c interface cmos compatible inputs mux rate: 65 logic supply voltage range v dd1 - v ss : 1.5 to 6 v voltage generator voltage range v dd2/2_hv - v ss : 2.4 to 5 v display supply voltage range v lcd - v ss : 7.0 to 16 v low power consumption, suitable for battery operated systems temperature compensation of v lcd interlacing for better display quality slim chip layout, suited for chip-on-glass applications. applications telecom equipment portable instruments point of sale terminals. general description the pcf8549 is a low power cmos lcd controller driver, designed to drive a graphic display of 65 rows and 102 columns. all necessary functions for the display are provided in a single chip, including on-chip generation of lcd supply and bias voltages, resulting in a minimum of external components and low power consumption. the pcf8549 interfaces to most microcontrollers via an i 2 c interface. packages the pcf8549u/2 is available as bumped die. sawn wafer as chip sorted in chip tray. for further details see section bonding pads. customized tcp upon request. ordering information type number package name description version pcf8549u/2/f1 tray chip with bumps in tray
1997 nov 21 3 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 block diagram column drivers hvgen 7 stages bias vol- tage gene- rator data latches row drivers shift register dual ported ram 65x102 bit oscillator timing generator display control logic iic interface sda_out sda scl vlcd2 vlcd1 c0 to c101 r0 to r64 osc t1 t3 t4 t2 vdd1 vdd2 vdd2_hv vss1 vss2 vss2_hv res sa0 t5 t6 t7 fig.1 block diagram.
1997 nov 21 4 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 pinning pin functions r0 to r64: row driver outputs these pads output the row signals. c0 to c101: column driver outputs these pads output the column signals. v ss1,2,2_hv : negative power supply rails negative power supplies. v dd1,2,2_hv : positive power supply rails v dd2 and v dd2_hv are the supply voltages for the internal voltage generator. both have to be on the same voltage and may be connected together outside of the chip. if the internal voltage generator is not used, they should be both connected to ground. v dd1 is used as power supply for the rest of the chip. this voltage can be a different voltage than v dd2 and v dd2_hv . v lcd1,2 : lcd power supply positive power supply for the liquid crystal display. if the internal voltage generator is used, the two supply rails v lcd1 and v lcd2 must be connected together. an external lcd supply voltage can be supplied using the v pad. in this case, v lcd1 has to be connected to ground, and the internal voltage generator has to be programmed to zero. if the pcf8549 is in power-down mode, the external lcd supply voltage has to be switched off. symbol description r0 to r64 lcd row driver outputs c0 to c101 lcd column driver outputs v ss1,2,2_hv negative power supply v dd1,2,2_hv supply voltage v lcd1,2 lcd supply voltage t1 test 1 input t2 test 2 output t3 test 3 i/o t4 test 4 i/o t5 test 5 input t6 test 6 input t7 test 7 input sda i 2 c data input scl i 2 c clock line sda_out i 2 c output sa0 least signi?cant bit of slave address osc oscillator res external reset input, low active
1997 nov 21 5 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 t1, t2, t3, t4, t5, t6 and t7: test pads t1, t3, t4, t5, t6 and t7 must be connected to v ss1 , t2 is to be left open. not accessible to user. sda/sda_out: i 2 cd ata lines output and input are separated. if both pads are connected together they behave like a standard i 2 c pad. scl: i 2 c clock signal input for the i 2 c-bus clock signal. sa0: s lave address with the sa0 pin two different slave addresses can be selected. that allows to connect two pcf8549 lcd drivers to the same i 2 c-bus. osc: oscillator when the on-chip oscillator is used this input must be connected to v dd1 . an external clock signal, if used, is connected to this input. res: reset this signal will reset the device. signal is active low. functional description block diagram functions o scillator the on-chip oscillator provides the clock signal for the display system. no external components are required and the osc input must be connected to v dd1 . an external clock signal, if used, is connected to this input. i 2 ci nterface the i 2 c interface receives and executes the commands sent via the i 2 c-bus. it also receives ram-data and sends them to the ram. during read access the 8-bit parallel data or the status register content is converted to a serial data stream and output via the i 2 c-bus. d isplay control logic the display control logic generates the control signals to read out the ram via the 101 bit parallel port. it also generates the control signals for the row, and column drivers. d isplay data ram (ddram) the pcf8549 contains a 65 102 bit static ram which stores the display data. the ram is divided into 8 banks of 102 bytes and one bank of 102 bits ((8 8+1) 102 bits). during ram access, data is transferred to the ram via the i 2 c interface. there is a direct correspondence between x-address and column output number. t iming generator the timing generator produces the various signals required to drive the internal circuitry. internal chip operation is not disturbed by operations on the i 2 c-bus. lcd row and column drivers the pcf8549 contains 65 row and 102 column drivers, which connect the appropriate lcd bias voltages to the display in accordance with the data to be displayed. figure 2 shows typical waveforms. unused outputs should be left unconnected.
1997 nov 21 6 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 fig.2 typical lcd driver waveforms. v lcd v 2 v 3 v 4 v 5 v ss row 0 r0 (t) v lcd v 2 v 3 v 4 v 5 v ss row 2 r2 (t) v lcd v 2 v 3 v 4 v 5 v ss col 0 c0 (t) v lcd v 2 v 3 v 4 v 5 v ss col 1 c1 (t) v lcd v 3 v lcd - v 2 0 v v 3 - v 2 v state1 (t) v lcd v 3 v lcd - v 2 0 v v 3 - v 2 v state2 (t) v state1 (t) v state2 (t) frame n+1 frame n v state1 (t) = c1(t) - r0(t) v state2 (t) = c1(t) - r2(t) v 4 - v 5 0 v v 5 v 4 - v lcd - v lcd v 4 - v 5 0 v v 5 v 4 - v lcd - v lcd v ss =0v 0 2 4 6 8 10 ... ... 64 1 3 5 7 9 ... ... 63 0 2 4 6 8 10 ... ... 64 1 3 5 7 9 ... ... 63
1997 nov 21 7 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 fig.3 ddram to display mapping. ddram bank 0 bank 1 bank 2 bank 3 bank 7 bank 8
1997 nov 21 8 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 addressing the display data ram of the pcf8549 is accessed as indicated in figs 3, 4, 4, 6 and 7. the display ram has a matrix of 65 102 bits. the columns are addressed by the address pointer. the address ranges are: x 0 to 101 (1100101b) and y 0 to 8 (1000b). addresses outside these ranges are not allowed. in vertical addressing mode (v = 1) the y address increments (see fig.7) after each byte. after the last y address (y = 8) y wraps around to 0 and x increments to address the next column. in horizontal addressing mode (v = 0) the x address increments (see fig.6) after each byte. after the last x address (x = 101) x wraps around to 0 and y increments to address the next row. after the very last address (x = 101 and y = 8) the address pointers wrap around to address (x = 0 and y = 0). the mx bit allows a horizontal mirroring: when mx = 1, the x address space is mirrored: the addres sx=0 is then located at the right side (column 101) of the display (see fig.4). when mx = 0 the mirroring is disabled and the address x = 0 is located at the left side (column 0) of the display (see fig.4). if the rm-bit (read-modify-write mode) is set, the address is only incremented after a write, otherwise the address is incremented after both read and write access to the display data ram.
1997 nov 21 9 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 d isplay data ram structure fig.4 ram format, addressing (mx = 0). msb lsb msb lsb 0 x-address 0 8 y-address 101 fig.5 ram format, addressing (mx = 1). msb lsb msb lsb 101 x-address 0 8 y-address 0
1997 nov 21 10 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 fig.6 sequence of writing data bytes into ram with horizontal addressing (v = 0). 0 x-address 101 y-address 8 0 012 102 103 104 204 205 206 306 307 308 408 409 410 510 511 512 612 613 614 714 715 716 816 817 818 917 fig.7 sequence of writing data bytes into ram with vertical addressing (v = 1). 0 y-address 8 09 1 10 2 3 4 5 6 7 8 917 101 0
1997 nov 21 11 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 ram access if the d/ c bit is 1 the ram can be accessed in both read and write access mode, depending on the r/ w bit. the data is written to the ram during the acknowledge cycle. i 2 c-bus interface characteristics of the i 2 c-bus the i 2 c-bus is for bi-directional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor. data transfer may be initiated only when the bus is not busy. b it transfer (see fig.9) one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high fig.8 read modify write access. set address set read modify write mode read data write data end finished? no yes period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. s tart and stop conditions (see fig.10) both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p). s ystem configuration (see fig.11) transmitter: the device which sends the data to the bus receiver: the device which receives the data from the bus master: the device which initiates a transfer, generates clock signals and terminates a transfer slave: the device addressed by a master multi-master: more than one master can attempt to control the bus at the same time without corrupting the message arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted synchronisation: procedure to synchronize the clock signals of two or more devices. a cknowledge (see fig.12) each byte of eight bits is followed by an acknowledge bit. the acknowledge bit is a high signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition.
1997 nov 21 12 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 fig.9 bit transfer. mbc621 data line stable; data valid change of data allowed sda scl fig.10 definition of start and stop conditions. mbc622 sda scl p stop condition sda scl s start condition fig.11 system configuration. mga807 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver fig.12 acknowledgement on the i 2 c-bus. mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
1997 nov 21 13 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 i 2 c-bus protocol the pcf8549 supports both read and write access. the r/ w bit is part of the slave address. before any data is transmitted on the i 2 c-bus, the device which should respond is addressed first. two 7-bit slave addresses (0111100 and 0111101) are reserved for the pcf8549. the least significant bit of the slave address is set by connecting the input sa0 to either logic 0 (v ss1 ) or 1(v dd1 ). the i 2 c-bus protocol is illustrated in fig.13. the sequence is initiated with a start condition (s) from the i 2 c-bus master which is followed by the slave address. all slaves with the corresponding address acknowledge in parallel, all the others will ignore the i 2 c-bus transfer. after acknowledgement, one or more command words follow which define the status of the addressed slaves. a command word consists of a control byte, which defines co and d/ c, plus a data byte (see fig.13 and table 1). the last control byte is tagged with a cleared most significant bit, the continuation bit co. after a control byte with a cleared co-bit, only data bytes will follow. the state of the d/ c-bit defines whether the data-byte is interpreted as a command or as ram-data.the control and data bytes are also acknowledged by all addressed slaves on the bus. after the last control byte, depending on the d/ c bit setting, either a series of display data bytes or command data bytes may follow. if the d/ c bit was set to 1, these display bytes are stored in the display ram at the address specified by the data pointer. the data pointer is automatically updated and the data is directed to the intended pcf8549 device. if the d/ c bit of the last control byte was set to 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. the acknowledgement after each byte is made only by the addressed slave. at the end of the transmission the i 2 c-bus master issues a stop condition (p). if the r/ w bit is set to one in the slave-address, the chip will output data immediately after the slave-address according to the d/ c bit, which was sent during the last write access. if no acknowledge is generated by the master after a byte, the driver stops transferring data to the master. fig.13 i 2 c-bus protocol. s 0 s aa a d c 1 control byte a data byte p a d c 0 control byte a data byte 111 0 01 slave address 2n > 0 bytes 1 byte n > 0 bytes msb................. lsb pcf8549 slave address co co acknowledgement from pcf8549 111 0 01 111 0 acknowledgement from pcf8549 acknowledgement from pcf8549 acknowledgement from pcf8549 acknowledgement from pcf8549 0 r w s 0 a s 0 s aa a a data byte p a a data byte slave address acknowledgement from master 111 0 01 acknowledgement from master acknowledgement from master acknowledgement from master 1 data byte data byte c o d c00 0 000 a control byte
1997 nov 21 14 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 instructions the instruction format is divided into two modes: if d/ c is set low, the status byte can be read or commands can be sent to the chip, depending on the r/ w signal. if d/ c is set high, the ddram will be accessed. every instruction can be sent in any order to the pcf8549. table 1 instruction set instruction d/ cr/ w command byte description db7 db6 db5 db4 db3 db2 db1 db0 h=0or1 nop 0 0 0 0 0 0 0 0 0 0 no operation function set 0 0 0 0 1 mx my pd v h power down control; entry mode; extended instruction set control (h) read status byte 0 1 pd x x d e mx my x reads status byte write data 1 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 writes data to ram read data 1 1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 reads data from ram h=0 set read modify write 0 0 0 0 0 0 0 0 1 rm sets the read-modify-write mode reserved 0 0 0 0 0 0 0 1 x x do not use display control 0 0 0 0 0 0 1 d 0 e sets display con?guration reserved 0 0 0 0 0 1 x x x x do not use set y address of ram 000100y 3 y 2 y 1 y 0 sets y-address of ram: 0 y 8 set x address of ram. 001x 6 x 5 x 4 x 3 x 2 x 1 x 0 sets x-address of ram: 0 x 101 h=1 reserved 0 0 0 0 0 0 0 0 0 1 do not use reserved 0 0 0 0 0 0 0 0 1 x do not use temperature control 0 0 0 0 0 0 0 1 tc 1 tc 0 set temperature coef?cient (tcx) reserved 0 0 0 0 0 0 1 x x x do not use bias system 0 0 0 0 0 1 0 bs 2 bs 1 bs 0 set bias system(bsx) reserved 0 0 0 1 x x x x x x do not use (reserved for test...) set v op 001v op6 v op5 v op4 v op3 v op2 v op1 v op0 write v op to register
1997 nov 21 15 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 table 2 explanations for symbols in table 1 external reset ( res) after power-on a reset pulse has to be applied immediately to the chip, as it is in an undefined state. a reset of the chip can be achieved with the external reset pin. after the reset the lcd driver is set to the following status: power down mode (pd = 1) all lcd-outputs at v ss (display off) read-modify-write mode is disabled (rm = 0) horizontal addressing (v = 0) normal instruction set (h = 0) normal display (mx = my = 0) display blank (e = d = 0) address counter x[6 : 0] = 0 and y[3 : 0] = 0 temperature coefficient (tc[1 : 0] = 0) bias system (bs[2 : 0] = 0) read-modify-write mode disabled (rm = 0) v lcd is equal to 0, the hv generator is switched off (v op [6:0]=0) after power-on, ram data are undefined; the reset signal does not change the content of the ram. set read-modify-write when rm = 0, the read-modify-write mode is disabled. the x/y-address counter is incremented after every read or write access to the display data ram. when rm = 1, the read-modify-write mode is enabled. in this mode the x/y-address is incremented only after a write access to the display data ram. the x/y-address will not be incremented after a read access to the ram. bit 0 1 reset state pd chip is active chip is in power down mode 1 v horizontal addressing vertical addressing 0 h use basic instruction set use extended instruction set 0 mx normal x-addressing x-address is mirrored 0 my display is not vertically mirrored display is vertically mirrored 0 rm read-modify-write mode is disabled read-modify-write mode is enabled 0 d and e 00 display blank d = 0 e=0 10 normal mode 01 all display segments on 11 inverse video mode tc[1 : 0] 00 v lcd temperature coef?cient 0 tc[1 : 0] = 00 01 v lcd temperature coef?cient 1 10 v lcd temperature coef?cient 2 11 v lcd temperature coef?cient 3 bs[2 : 0] bias system bs[2 : 0] = 000
1997 nov 21 16 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 function set pd ( power down ) all lcd outputs at v ss (display off) bias generator and v lcd generator off oscillator off (external clock possible) v lcd can be disconnected parallel bus, command, etc. function ram contents not cleared; ram data can be written. v when v = 0, the horizontal addressing is selected. the data is written into the ram as shown in fig.6. when v = 1, the vertical addressing is selected. the data is written into the ram as shown in fig.7. h when h = 0 the commands display control, set y address and set x address can be performed, when h = 1 the other commands can be executed. the commands write data and function set can be executed in both cases. mx when mx = 0, the display is written from left to right (x = 0 is on the left side, x = 100 is on the right side of the display). when mx = 1 the display is written from right to left (x = 0 is on the right side, x = 100 is on the left side of the display). my when my = 1, the display is mirrored vertically. display control d and e the bits d and e select the display mode (see table 2). set y address of ram y[3 : 0] defines the y address vector address of the ram. table 3 x-/y-address range in bank 8 only the msb is accessed. set x address of ram the x address points to the columns. the range of x is 0 to 101(65 hex). temperature control due to the temperature dependency of the liquid crystals viscosity the lcd controlling voltage v lcd must be increased with lower temperature to maintain optimal contrast. there are 4 different temperature coefficients available in the yyyy 3 210 content allowed x-range 0000 bank 0 (display ram) 0 to 101 0001 bank 1 (display ram) 0 to 101 0010 bank 2 (display ram) 0 to 101 0011 bank 3 (display ram) 0 to 101 0100 bank 4 (display ram) 0 to 101 0101 bank 5 (display ram) 0 to 101 0110 bank 6 (display ram) 0 to 101 0111 bank 7 (display ram) 0 to 101 1000 bank 8 (display ram) 0 to 101
1997 nov 21 17 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 pcf8549 (see fig.14). the coefficients are selected by the two bits tc[1 : 0]. table 6 shows the typical values of the different temperature coefficients. the coefficients are proportional to the programmed v lcd . bias value: the bias voltage levels are set in the ratio of r - r - nr - r - r giving a bias system. the resulting bias levels are shown in table 5. different multiplex rates require different factors n (see table 4). this is programmed by bs[2 : 0]. for mux 1 : 65 the optimum bias value n is given by: resulting in 1 9 bias. table 4 programming the required bias system bs[2] bs[1] bs[0] n b (res. count) mux rate 0007 11 1:100 0016 10 1:81 0105 9 1:64 0114 8 1:49 1003 7 1:36 fig.14 temperature coefficients. 16 o c(typ) v lcd temperature 1 n4 + ------------ - nm3 C 65 3 C 5.06 5 == ==
1997 nov 21 18 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 table 5 lcd bias voltage set v op value: the operation voltage v lcd can be set by software. the generated voltage is dependent of the temperature, the programmed temperature coefficient (tc), and the programmed voltage at reference temperature (t cut ). (1) the voltage at reference temperature (v lcd (t=t cut )) can be calculated as: (2) the parameters are explained in table 6. the maximum voltage that can be generated is depending on the v dd2/2_hv voltage and the display load current. the relation ship is shown in fig.16. the charge pump is turned off if vop[6 : 0] is set to zero. for mu x 1 : 65 the optimum operation voltage of the liquid can be calculated as: where v th is the threshold voltage of the liquid crystal material used. 1012 6 1:24 1101 5 1:16 1110 4 1:9 symbol bias voltages v1 v lcd v2 (b-1)/b v lcd v3 (b-2)/b v lcd v4 2/b v lcd v5 1/b v lcd v6 v ss bs[2] bs[1] bs[0] n b (res. count) mux rate v lcd a vop + b () tt cut C () tc + = v lcd avop + b () = v lcd 165 + 21 1 65 ---------- C ? ?? -------------------------------------- - v th 6.85 v th = =
1997 nov 21 19 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 table 6 typical values for parameters for the hv-generator programming symbol value unit a 7.06 v b 0.06 v t cut 16 0 c tc 00 v/ o c 01 v/ o c 10 v/ o c 11 v/ o c 0.142 10 3 C v lcd tt cut = () C 1.3 10 3 C v lcd tt cut = () C 2.467 10 3 C v lcd tt cut = () C 3.483 10 3 C v lcd tt cut = () C fig.15 v op programming of pcf8549. v op [6:0] (programmed) [00 hex ... 7f hex] 00 01 02 03 04 05 06 07 08 09 0a ... a v lcd b
1997 nov 21 20 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 limiting values in accordance with the absolute maximum system (iec 134); all voltages referred to v ss = 0v unless otherwise specified. notes 1. stresses above those listed under limiting values may cause permanent damage to the device. 2. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted. 3. with external lcd supply voltage external supplied (voltage generator disabled) . v ddmax (v dd2 ,v dd2_hv ) is 5v if lcd supply voltage is internally generated (voltage generator enabled). handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices (see handling mos devices). the pcf8549 withstands the following stress: approximately 1.0kv human body model approximately 150v machine model symbol parameter min max unit v dd supply voltage range -0.5 +7 v v lcd supply voltage range lcd -0.5 +17 v i ss supply current -50 50 ma v i /v o input/output voltage range -0.5 v dd +0.5 v v olcd lcd output voltage range -0.5 v lcd +0.5 v i i dc input current -10 10 ma i o dc output current -10 10 ma p tot power dissipation per package - 300 mw p o power dissipation per output - 50 mw t amb operating ambient temperature. range -40 +85 ? c t stg storage temperature range -65 +150 c
1997 nov 21 21 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 dc characteristics table 7 v dd1 = 1.5 to 6 v; v dd2/2_hv = 2.4 to 5.0 v; v dd2 = v dd2_hv ; v ss1 = v ss2 = v ss2_hv = 0 v; v lcd =7to16v; t amb = - 40 to +85 c; unless otherwise speci?ed. note 1. when a display is connected the i vdd2_hv increases with 7 x display load current due to 7 stage charge pump. 2. with external v lcd , the display load current does not translate into increased i vdd2_hv . 3. for tc1, tc2 and tc3 4. the maximum possible vlcd voltage that may be generated is dependent on voltage (v dd2/2_hv ), temperature and (display) load. 5. v dd2 v dd2_hv connected together 6. difference to the theoretical value given by equation 1 symbol parameter conditions min typ max unit v dd1 logic supply voltage range 1.5 3 6 v v dd2, v dd2_hv hv generator supply range 2.4 5 v i vdd1 supply current internal v lcd v lcd = 10.0v; f scl = 0; display load = 0; 30 80 m a i vdd2/2_hv supply current internal v lcd v lcd = 10.0v; f scl = 0; display load = 0; (1)(5) 600 1200 m a i vdd1 supply current external v lcd v lcd = 10.0v; f scl = 0; display load = 0; 30 80 m a i vdd2/2_hv supply current external v lcd v lcd = 10.0v; f scl = 0; display load = 0; (2)(5) 010 m a i vdd1 supply current power-down mode; v lcd = 0v; f scl = 0; display load = 0 0.5 10 m a i lcd supply current external v lcd v lcd = 10 v; f scl = 0, display load = 0; (2) 50 130 m a v lcd(tol) v lcd tolerance internal generated v dd = 2.7v; v lcd = 10v; f scl = 0; display load = 0; (3)(4)(6) +/- 500 mv v il low level input volt- age v ss 0.3v dd v v ih high level input voltage 0.7 v dd v dd v i ol low level output current (sda) v ol = 0.4v; v dd1 =5v 3.0 ma i l leakage current v i = v dd1 or v ss1 -1 +1 m a r row row output resis- tance r0 to r64 12 20 kohm r col column output resis- tance c0 to c101 12 20 kohm
1997 nov 21 22 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 ac characteristics table 8 v dd1 = 1.5 to 6 v; v dd2/2_hv = 2.4 to 5.0 v; v dd2 = v dd2_hv ; v ss1 = v ss2 = v ss2_hv = 0 v; v lcd =7to16v; t amb = - 40 to +85 c; unless otherwise speci?ed. note 1. 2. duty cycle of 50 +/-5%. 3. the rise and fall times specified here refer to the driver device (i.e. not pcf8549) and are part of the general fast i 2 c-bus specification. when pcf8549 asserts an acknowledge on sda, the minimum fall time is 10ns. c b = capacitive load per bus line. 4. the device inputs sda and scl are filtered and will reject spikes on the bus lines of width < t sw(max) . 5. not tested in production 6. only for vdd1= 2v to 6v symbol parameter conditions min. typ. max. unit f osc oscillator frequency 19 32 64 khz f ext external clock frequency (2) 10 32 64 khz t start oscillator start up time (5) - 450 1600 us f frame frame frequency f ext = 32 khz; (1) - 62 - hz t vhrl vdd to res low (5) 1ms t pwres reset low pulse width 400 -- ns i 2 c timing characteristics f sclk scl clock frequency (6) dc - 400 khz t low scl clock low period 1.3 -- us t high scl clock high period 0.6 -- us t su;data data set-up time 100 -- ns t hd;data data hold time 0 - 0.9 us t r scl and sda rise time (3) 20 + 0.1 cb - 300 ns t f scl and sda fall time (3) 20 + 0.1 cb - 300 ns c b capacitive load represented by each bus line -- 400 pf t su;sta setup time for a repeated start con- dition 0.6 -- us t hd;sta start condition hold time 0.6 -- us t su;dat data set-up time 100 -- ns t hd;dat data hold-time 0 -- ns t su;sto setup time for stop condition 0.6 -- us t sw tolerable spike width on bus (4) -- 50 ns t buf bus free time between a stop and start condition 1.3 -- us f frame f ext 520 ---------- - =
1997 nov 21 23 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 typical characteristics reset 0v 1v 2v 3v 4v 5v 12v 13v 14v 15v 16v i=0ua i=10ua i=20ua i=40ua vdd2, vdd2_hv vlcd fig.16 vlcd dependency of vdd2, vdd2_hv and load current. programmed vlcd=15.8v (@ room temperature in special test mode) fig.17 reset timing. t pwres res vdd t vhrl
1997 nov 21 24 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 application information table 9 programming example for pcf8549 step display operation db7 db6 db5 db4 db3 db2 db1 db0 1i 2 c start 2 0 1 1 1 1 0 0 0 slave address for write 3 0 0 0 0 0 0 0 0 control byte with cleared c o bit and d/ c set to 0. 4 0 0 1 0 0 0 0 1 function set pd = 0; v = 0; select extended instruction set (h = 1 mode) 5 0 0 0 1 0 0 1 0 set bias system 2. this is the recommended bias system for a multiplex rate 1:65 6 1 1 1 0 1 0 1 0 set v op v op is set to a +16 b [v]. please note: the required voltage is depending on the liquid. 7 0 0 1 0 0 0 0 0 function set pd = 0; v = 0; select normal instruction set (h = 0 mode) 8 0 0 0 0 1 1 0 0 display control set normal mode (d = 1 and e = 0) 9i 2 c start restart: to write into the display ram the d/ c must be set to 1; therefore a control byte is needed. 10 0 1 1 1 1 0 0 0 slave address for write 11 0 1 0 0 0 0 0 0 control byte with cleared c o bit and d/ c set to 1. 12 1 1 1 1 1 0 0 0 data write y and x are initialized to 0 by default, so they arent set here 13 1 0 1 0 0 0 0 0 data write 14 1 1 1 0 0 0 0 0 data write
1997 nov 21 25 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 15 0 0 0 0 0 0 0 0 data write 16 1 1 1 1 1 0 0 0 data write 17 0 0 1 0 0 0 0 0 data write 18 1 1 1 1 1 0 0 0 data write 19 i 2 c start restart 20 0 1 1 1 1 0 0 0 slave address for write 21 1 0 0 0 0 0 0 0 control byte with set c o bit and d/ c set to 0. 22 0 0 0 0 1 1 0 1 display control set inverse video mode (d = 1 and e = 1) 23 1 0 0 0 0 0 0 0 control byte with set c o bit and d/ c set to 0. 24 1 0 0 0 0 0 0 0 set x address of ram set address to 0000000 25 1 1 0 0 0 0 0 0 control byte with set c o bit and d/ c set to 1. 26 0 0 0 0 0 0 0 0 data write 27 0 0 0 0 0 0 0 0 control byte with cleared c o bit and d/ c set to 0. 28 1 0 0 0 0 0 0 0 set x address of ram set address to 0000000 29 0 0 0 0 0 0 0 1 set read modify write mode step display operation db7 db6 db5 db4 db3 db2 db1 db0
1997 nov 21 26 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 application information 30 i 2 c start restart 31 0 1 1 1 1 0 0 0 slave address for write 32 1 1 0 0 0 0 0 0 control byte with set c o bit and d/ c set to 1. 33 i 2 c start restart 34 0 1 1 1 1 0 0 1 slave address for read 35 1 0 0 0 0 0 0 0 read data from address 0000000 36 1 0 0 0 0 0 0 0 read data from address 0000000 again. master does not send an acknowledge to stop the read access. 37 i 2 c start restart 38 0 1 1 1 1 0 0 0 slave address for write 39 1 1 0 0 0 0 0 0 control byte with set c o bit and d/ c set to 1. 40 1 1 1 1 1 0 0 0 write data 41 1 0 0 0 0 0 0 0 control byte with set c o bit and d/ c set to 0. 42 i 2 c start restart 43 0 1 1 1 1 0 0 1 slave address for read 44 1 0 0 0 0 0 0 0 read status byte step display operation db7 db6 db5 db4 db3 db2 db1 db0
1997 nov 21 27 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 pcf8549 sda sda_out scl microcontroller scl sda vdd1 vdd1 fig.18 application diagram: connecting the i2c interface
1997 nov 21 28 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 the pinning of the pcf8549 is optimized for single plane wiring e.g. for chip-on-glass display modules. display size: 65 102 pixels. chip information the pcf8549 is manufactured in n-well cmos technology. the substrate is on v ss potential. fig.19 application diagram: connecting the power supplies display 102x65 pcf8549 vss v lcd c1 vdd2 vdd2_hv c2 c3 c4 i/o c 1 100nf 3 c 2 100nf 3 c 4 100nf 3 c 3 1uf 3 33 32 102 13 vdd1 vdd1 vss C 1.5v 3 vdd2 vss C 2.4v 3 vdd2hv vdd2 =
1997 nov 21 29 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 bonding pads value unit pad pitch min. 100 m m pad size, alumin. 80 100 m m passivation. 48 78 m m bumps 60 ( 6) 90 ( 6) 17.5 ( 5) m m wafer thickness 380 ( 25) m m
1997 nov 21 30 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 11 1 1 1 11 1 11 1 1 1 1 11 11 1 1 1 1 1 1 1 1 1 1 1 1 11 1 1 1 11 1 11 11 11 11 11 11 1 1 1 11 1 1 1 1 1 1 11 1 1 11 1 1 1 1 1 1 1 11 1 1 11 1 1 1 1 1 11 1 1 11 1 1 11 1 1 1 1 11 1 1 11 1 1 11 1 1 11 1 1 1 1 11 1 1 1 11 1 1 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 1 1 11 1 1 11 1 1 11 1 1 1 1 1 1 1 11 1 1 11 1 1 11 1 1 11 1 1 1 1 11 1 1 11 1 1 1 1 11 1 1 11 1 1 1 1 11 1 1 11 1 1 1 1 1 11 1 1 11 1 1 11 1 1 1 1 1 1 1 11 1 1 11 1 1 1 1 11 1 1 11 1 1 11 1 1 11 11 1 1 1 1 1 11 11 1 1 1 1 11 fig.20 pads. r31 r1 osc vdd1 vdd2 vdd2_hv res sda_out scl sda t2 sa0 t7 t6 t5 t4 t3 t1 vss1 vss2_hv vss2 vlcd_1 vlcd2 r0 r30 dummy dummy dummy r63 r33 c0 c101 r32 r34 r64 dummy recognition pattern recognition pattern pad 1 pc8549 16.39mm 2.74mm
1997 nov 21 31 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 table 10 bonding pad locations (dimensions in um). pad pad name x y 1 t2 7359.5 2462 2 sa0 6958 2462 3 t7 6679 2462 4 t6 6400 2462 5 t5 6121 2462 6 t4 5841.5 2462 7 t3 5431.5 2462 8 t1 5022 2462 9 vss1 4724 2458 10 vss1 4624 2458 11 vss2_hv 4359 2458 12 vss2_hv 4259 2458 13 vss2_hv 4159 2458 14 vss2 3458.5 2458 15 vlcd1 2580 2462 16 vlcd2 2294 2462 17 row<0> 1870 2437 18 row<2> 1770 2437 19 row<4> 1670 2437 20 row<6> 1570 2437 21 row<8> 1470 2437 22 row<10> 1370 2437 23 row<12> 1270 2437 24 row<14> 1170 2437 25 row<16> 1070 2437 26 row<18> 970 2437 27 row<20> 870 2437 28 row<22> 770 2437 29 row<24> 670 2437 30 row<26> 570 2437 31 row<28> 470 2437 32 row<30> 370 2437 33 dummy 4 270 2437 34 dummy 5 170 2437 35 dummy 6 70 2437 36 dummy 3 70 84 37 dummy 2 170 84 38 dummy 1 270 84 39 row<64> 370 84 40 row<62> 470 84 41 row<60> 570 84 42 row<58> 670 84 43 row<56> 770 84 44 row<54> 870 84 45 row<52> 970 84 46 row<50> 1070 84 47 row<48> 1170 84 48 row<46> 1270 84 49 row<44> 1370 84 50 row<42> 1470 84 51 row<40> 1570 84 52 row<38> 1670 84 53 row<36> 1770 84 54 row<34> 1870 84 55 row<32> 2137 84 56 col<101> 2812 84 57 col<100> 2914 84 58 col<99> 3014 84 59 col<98> 3114 84 60 col<97> 3214 84 61 col<96> 3314 84 62 col<95> 3560 84 63 col<94> 3660 84 64 col<93> 3760 84 65 col<92> 3860 84 66 col<91> 3960 84 67 col<90> 4060 84 68 col<89> 4160 84 69 col<88> 4260 84 70 col<87> 4360 84 71 col<86> 4460 84 72 col<85> 4560 84 73 col<84> 4660 84 74 col<83> 4760 84 75 col<82> 4860 84 76 col<81> 4960 84 77 col<80> 5060 84 78 col<79> 5306 84 79 col<78> 5406 84 80 col<77> 5506 84 pad pad name x y
1997 nov 21 32 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 81 col<76> 5606 84 82 col<75> 5706 84 83 col<74> 5806 84 84 col<73> 5906 84 85 col<72> 6006 84 86 col<71> 6106 84 87 col<70> 6206 84 88 col<69> 6306 84 89 col<68> 6406 84 90 col<67> 6506 84 91 col<66> 6606 84 92 col<65> 6706 84 93 col<64> 6806 84 94 col<63> 7052 84 95 col<62> 7152 84 96 col<61> 7252 84 97 col<60> 7352 84 98 col<59> 7452 84 99 col<58> 7552 84 100 col<57> 7652 84 101 col<56> 7752 84 102 col<55> 7852 84 103 col<54> 7952 84 104 col<53> 8052 84 105 col<52> 8152 84 106 col<51> 8252 84 107 col<50> 8352 84 108 col<49> 8452 84 109 col<48> 8552 84 110 col<47> 8798 84 111 col<46> 8898 84 112 col<45> 8998 84 113 col<44> 9098 84 114 col<43> 9198 84 115 col<42> 9298 84 116 col<41> 9398 84 117 col<40> 9498 84 118 col<39> 9598 84 119 col<38> 9698 84 120 col<37> 9798 84 pad pad name x y 121 col<36> 9898 84 122 col<35> 9998 84 123 col<34> 10098 84 124 col<33> 10198 84 125 col<32> 10298 84 126 col<31> 10544 84 127 col<30> 10644 84 128 col<29> 10744 84 129 col<28> 10844 84 130 col<27> 10944 84 131 col<26> 11044 84 132 col<25> 11144 84 133 col<24> 11244 84 134 col<23> 11344 84 135 col<22> 11444 84 136 col<21> 11544 84 137 col<20> 11644 84 138 col<19> 11744 84 139 col<18> 11844 84 140 col<17> 11944 84 141 col<16> 12044 84 142 col<15> 12290 84 143 col<14> 12390 84 144 col<13> 12490 84 145 col<12> 12590 84 146 col<11> 12690 84 147 col<10> 12790 84 148 col<9> 12890 84 149 col<8> 12990 84 150 col<7> 13090 84 151 col<6> 13190 84 152 col<5> 13290 84 153 col<4> 13390 84 154 col<3> 13490 84 155 col<2> 13590 84 156 col<1> 13690 84 157 col<0> 13790 84 158 row<33> 14204 84 159 row<35> 14304 84 160 row<37> 14404 84 pad pad name x y
1997 nov 21 33 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 161 row<39> 14504 84 162 row<41> 14604 84 163 row<43> 14704 84 164 row<45> 14804 84 165 row<47> 14904 84 166 row<49> 15004 84 167 row<51> 15104 84 168 row<53> 15204 84 169 row<55> 15304 84 170 row<57> 15404 84 171 row<59> 15504 84 172 row<61> 15604 84 173 row<63> 15704 84 174 dummy 7 15804 84 175 dummy 8 15904 84 176 dummy 9 16004 84 177 dummy 12 15961 2437 178 dummy 11 15861 2437 179 dummy 10 15761 2437 180 row<31> 15661 2437 181 row<29> 15561 2437 182 row<27> 15461 2437 183 row<25> 15361 2437 184 row<23> 15261 2437 185 row<21> 15161 2437 186 row<19> 15061 2437 187 row<17> 14961 2437 188 row<15> 14861 2437 189 row<13> 14761 2437 190 row<11> 14661 2437 191 row<9> 14561 2437 192 row<7> 14461 2437 193 row<5> 14361 2437 194 row<3> 14261 2437 195 row<1> 14161 2437 196 osc 13738 2462 197 vdd1 13147 2461 198 vdd1 13047 2461 199 vdd1 12947 2461 200 vdd2 12145 2461 pad pad name x y 201 vdd2_hv_i n 11145 2461 202 vdd2_hv_i n 11045 2461 203 vdd2_hv_i n 10945 2461 204 res_b_in 10627 2462 205 sda_out 10333.5 5 2462 206 sda_in 9412.4 2462 207 sda_in 9212.4 2462 208 scl_in 8256.8 2462 209 scl_in 8056.8 2462 recpat c1 16275 2437 recpat c2 2301 80 recpat f 304 1824 pad pad name x y
1997 nov 21 34 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1997 nov 21 35 philips semiconductors product speci?cation 65 102 pixels matrix lcd driver pcf8549 notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca56 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 160 1010, fax. +43 160 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 417067/1200/01/pp36 date of release: 1997 nov 21 document order number: 9397 750 03044

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